1. Field of the Invention
The present invention relates, in general, to timing apparatus and, more particularly, to a programmable timing apparatus for providing a number of precisely synchronized timing signals.
2. Statement of the Problem
Programmable timing units, also called digital delay generators, find many uses where it is desired to produce a number of signals at precise time intervals. For example, these devices are used for timing lasers, conducting electronics and materials research experiments, and other applications requiring very precise timing.
Typically, digital delay generators produce delay intervals from zero to many seconds with resolution on the order of one part in 10.sup.-8 and increment intervals as small as a few nanoseconds (one nanosecond or "ns" is 10.sup.-9 second). Conventional methods for generating timing signals having this level of resolution use an electronic timing oscillator directly controlled by a quartz crystal. Such an oscillator can operate at a frequency from 10 kilohertz (KHz) to several 100 megahertz (MHz). The frequency is determined primarily by the physical dimensions of the crystal.
A common variation in this conventional technique uses a timing oscillator that is controlled indirectly by a crystal oscillator using a phase-locked loop. The timing oscillator does not have to operate at the same frequency as the crystal oscillator in a phase-locked loop circuit, and accordingly, a wider choice of crystal oscillators is possible. The timing interval of the delay in both cases is generally determined by counting cycles of the timing oscillator.
In practical timing digital delay generators, the frequency of the timing oscillator is usually not much greater than 100 MHz. This is because readily available integrated circuits that are required to count the timing oscillator cycles do not operate well above 100 MHz. Since the smallest incremental interval determinable by counting cycles is one cycle, a 100-MHz oscillator will provide incremental intervals of 10 ns which is the period of a 100-MHz signal.
Various systems have been used to generate a sequence of timing signals of variable signal-to-signal interval by programming digital counters to produce the timing signals at predetermined counts of a clock. Tapped delay lines have also been used to delay the signals relative to the start of a timing sequence. The timing signal interval resolution in such systems has been limited by the clock resolution.
One timing signal generator is disclosed in U.S. Pat. No. 4,231,104 entitled "Generating Timing Signals" issued to St. Claire. This system uses a programmable counter in combination with a tapped delay line to produce a chain of pulses that are asynchronous with (i.e., not an integer multiple of) the clock period. The accuracy of such systems, however, is dependent on the accuracy of the tapped delay lines used. That is, a higher-resolution delay line would have a correspondingly smaller range of settings to which the timing signal can be set. Also, depending on the number of delay taps, it may be difficult to obtain certain timing signal period settings.
One way to alleviate these shortcomings is to use a higher-frequency clock. However, as discussed above, counters suitable for use at such high clock frequencies are complex and costly to fabricate. Also, the distribution of high-frequency clock signals throughout a timing system requires an expensive and complex high bandwidth transmission system. For this reason, it is desirable to distribute a lower-frequency clock throughout the system and remote portions of the timing unit. It is desirable to use system clocks with speeds less than 100 MHz.
Another problem of existing timing units is that they provide few delayed outputs. Typically 2 to 4 outputs are provided where each of the delays is synchronized either to a single clock or to one of the other delayed outputs. Hence, a user is very limited in his ability to configure the delay of the timing unit to provide a timing signal precisely when it is desired relative to any of the other delayed outputs. The limited number of outputs requires multiple timing units to be coupled together in series when more delayed output signals are required. This increases expense and complexity of the system as well as leading to inaccuracies caused by the connections between the timing units themselves.
There is a demand for timing units that have great accuracy and precision in the range of one nanosecond. However, existing timing units are relatively inaccurate in the range of one nanosecond. Even timing units or programmable delay lines that are specified with one-nanosecond resolution are accurate only plus or minus one nanosecond, or 100% error. Also, conventional timing units that offer nanosecond resolution can do so only through carefully constructed hardwired circuits, which makes them more difficult to configure to meet particular needs of the user.
One programmable timing unit is shown in U.S. Pat. No. 4,458,165 issued to Jackson on Jul. 3, 1984. This timing apparatus uses a pair of multiplexers and a fixed value delay device between the multiplexers in a negative feedback path. By selecting the signal path using the multiplexers, a limited number of different delay durations are provided between the input and output terminals. This method results in a programmable delay line, but only provides one output and a limited number of delay times.
U.S. Pat. No. 4,564,953 issued to Werking on Jan. 14, 1986, uses a high-speed (500-MHz) clock that is coupled to a two-stage counter. A delay is created by varying the modulus of the counter. The period resolution is limited to the resolution of the high-frequency clock, however.
U.S. Pat. No. 4,719,375 issued to Martin on Jan. 12, 1988, shows a digital delay timer that uses a series of three programmable delays to interpolate a delay between clock pulses of a system clock. The system, however, offers high precision for only a single delay interval and must be fine-tuned to produce other delays. No means is provided for easily switching between delay intervals. Moreover, although the system provides a delayed output, there is no way to programmably couple the delayed output to desired circuitry without using additional switching apparatus.
U.S. Pat. No. 4,968,907 issued to Pepper on Nov. 6, 1990, discloses a digital delay generator that uses an analog ramp method of timing and is susceptible to long-term temperature drifts associated with analog circuity. Analog circuitry also makes it more difficult to program the delay generator by using available digital microprocessors.
Accordingly, there remains a need for a programmable timing unit with great flexibility allowing the user to configure the delay interval over a wide range of times with great precision. A need also exists for a timing unit that can provide a number of delayed output signals where each delayed output signal occurs at a precise time after a triggering event or at a precise time with respect to a previous delayed output signal. Further, a need exists for a timing unit that uses a relatively low-speed clock and provides higher resolution than that clock without sacrificing accuracy in the timing interval.
3. Solution to the Problem
The present invention provides a solution to the above-mentioned problems by providing a programmable timing unit using a single relatively low frequency system clock to generate a number of timing signals that are synchronized with each other. Each of the number of timing circuits can be programmed to trigger anywhere along a time line defined by the low-frequency system clock. The programmable timing circuits are able to interpolate between clock pulses once they are triggered.
The outputs of the timing circuits are programmably coupled to any of the number of function circuits. The timing unit output signals are generated by the function circuits. Errors and inaccuracies caused by interconnections are minimized by positioning components near each other. Fixed time delays introduced by the distance between components are calibrated out. Because both the timing circuits and the matrix circuits are programmable, any number of timing outputs can be provided. Each timing output can be connected at the desired time to a desired function circuit.